[PDF] MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems | Semantic Scholar (2024)

A behavior-level modeling framework for memristor-based training-in-memory architectures, called MNSIM-TIME, which supports configurable architecture design and fast hardware performance modeling, which helps researchers to realize efficient design space exploration in the early architecture design stage.

A comprehensive framework for co-designing the software and hardware for deep neural networks (DNN) based on memristive and memcapacitive crossbars while considering various non-idealities is introduced, taking into account device-level factors.

A reliability-aware training framework, containing network splitting/merging analysis and a PIM-based non-uniform activation quantization scheme, can improve the energy efficiency by reducing the ADC resolution requirements in memristor crossbars and provide a general modeling method for PIM architecture design and computation data flow.

In this work, a non-idealities aware software-hardware co-design framework for deep neural network (DNN) implemented on memristive crossbar is presented and can effectively mitigate the impact of thesenon-ideal factors and reduce the inference accuracy degradations.

Three key aspects of neuromorphic computation are addressed in this article, and system, architecture, circuit, and device simulators for this new computing paradigm are all being investigated.

A device-architecture-algorithm co-design simulator is proposed to provide guidelines for designing CIM systems and a CIM compiler was proposed to optimize the on-chip dataflow.

Layer ensemble averaging is proposed and experimentally demonstrates, a technique to map pre-trained neural network solutions from software to defective hardware crossbars of emerging memory devices and reliably attain near-software performance on inference.

A physics-based compact model of reliability degradation in analog resistive random access memory (RRAM) and a device-to-system simulation framework for the computation-in-memory (CIM) system is developed, providing a useful device–system codesign tool for developing large-scale CIM systems with high performance.

It is demonstrated that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.

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A simulation platform for the memristor-based neuromorphic system, called MNSIM, which can optimize the design and estimate the tradeoff relationships among different performance metrics for users and achieves over 7000 times speed-up than SPICE simulation.

A defect engineering approach using the atomic layer deposition method to localize the oxygen vacancies (Vo) formation uniformly, which results in uniform multi-weak-filaments formed in RRAM devices, and the variation of linearity and dynamic ON/OFF ratio in different devices can be suppressed using the proposed method.

A flexible simulation framework that simulates the error rates of every sum-of-products computation in the memristor-based accelerator and injects the errors in the targeted TensorFlow-based neural network model, DL-RSIM, which can be incorporated with any deep learning neural network implemented by Tensor Flow.

This work provides a joint device-circuit-algorithm analysis and proposes the corresponding design guidelines for the NPU design of RRAM based neural-processing-unit.

NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.

This work analyzes the impact of reliability in "analog" synaptic devices, and analog-to-digital converter quantization effects on the inference accuracy, and benchmark CIM accelerators based on SRAM and versatile emerging devices, revealing the benefits of high on-state resistance.

The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range, and makes the proposed folding-flash ADC attractive for the next-generation wireless applications.

This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner.

An energy-efficient quantized and regularized training framework for PIM accelerators, which consists of a PIM-based non-uniform activation quantization scheme and an energy-aware weight regularization method that can improve the energy efficiency of PIM architectures by reducing the ADC resolution requirements and training low energy consumption CNN models for Pim, with little accuracy loss.

A configurable multi-precision CNN computing framework based on single bit RRAM, which consists of an RRAM computing overhead aware network quantization algorithm and a configurablemulti-pre precision CNN computing architecture based on one bit R RAM.

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